The present invention relates to a class D amplifier circuit and, in particular, relates to a class D amplifier circuit which can realize the reduction of distortion and power loss at the time of inputting a small signal.
The class D amplifier circuit converts an input signal into a pulse width modulation signal having constant amplitude and amplifies the power of the pulse width modulation signal. The class D amplifier circuit is used for amplifying the power of an audio signal. Since the class D amplifier circuit operates based on binary values, transistor loss can be reduced to a large extent and so a high efficiency can be realized advantageously.
Such a kind of the class D amplifier circuit includes an integration circuit for integrating an input signal, a comparison circuit for comparing the output signal of the integration circuit with a predetermined triangular signal, and a pulse width amplifier for amplifying the output signal of the comparison circuit to thereby output as pulse signal. The output signal of the pulse width amplifier is fed back to the input side of the integration circuit. The output signal of the pulse width amplifier passes a low pass filter configured by a coil and a capacitor and so obtained as an analog signal for driving a load such as a speaker. In recent years, a filter-less class D amplifier circuit has been realized in which a low-pass filter is eliminated.
As described in JP-A-2006-42296, in order to avoid the power loss at the time where the input signal has no signal component, that is, at the time of no input-signal, the class D amplifier circuit employs a differential input system and a delay circuit to thereby set a duty ratio of an output pulse at the time of no input-signal to several percent. FIG. 4 is a block diagram showing such a class D amplifier circuit 200. For the sake of convenience, this figure shows only the main portion of the amplifier, and a feedback circuit and an integration circuit etc. are omitted. The class D amplifier circuit 200 compares an input signal Vi+ to a positive input terminal and an input signal Vi− to a negative input terminal with a triangular wave output from a triangular wave generation circuit 20 by using comparators 12a, 12b, respectively to thereby pulse-width modulate the input signals.
As shown in FIG. 5, at the time of no input-signal, each of the output signal A of the comparator 12a and the output signal B of the comparator 12b is a pulse signal having a duty ratio of 50%. When these pulse signals are subjected to the logical operation by using a circuit configured by inverters 13a, 13b and NAND circuits 14a, 14b, each of the output signal OutP of a positive output terminal and the output signal OutM of a negative output terminal output via an output stage circuit 40 does not contain any output pulse. Thus, the power loss at the time of no input-signal can be reduced. However, in general, since there arises a dead zone near the input crossover due to the accuracy etc. of the comparators 12, the pulse signal output disappears or distortion appears at the time of inputting no signal or a small signal. Thus, the class D amplifier circuit 200 employs a delay circuit 30 having a delay amount W to thereby generate a signal Bd. Therefore, as shown in FIG. 5, since a pulse signal having a pulse width W is output as each of the output signals OutP, OutM at the time of no input-signal, the modulation width can be accurately reflected and the distortion can be reduced at the time of the small input signal.
As explained above, the distortion at the time of the small input signal can be reduced by outputting the pulse having the width W at the time of no input-signal. However, since a current flows into a load such as a speaker when the pulse width W of the output pulse is large, there arises the power loss and also heat generated by such the power loss can not be neglected. Accordingly, the pulse width W of the output pulse is required to be as small as possible, preferably.
Although the output pulses are output to the load (not shown) via the output stage circuit 40, in general the output stage circuit 40 is configured by buffers which are connected in a multi-stage manner. In this case, in order to transmit the output pulse correctly, the output pulse of the certain buffer is required to exceed the threshold voltage of the buffer of the next-stage.
However, if the waveform of the output pulse is dulled due to the input capacity of the buffer, the pulse cannot be transmitted sufficiently to the buffer of the next stage, there may arise a case that there appears no output pulse. When the output pulse disappears, the distortion is generated at the time of the small input signal. On the other hand, if the delay amount W of the delay circuit 30 is set to be large, at the time that the delay amount of the output stage circuit 40 becomes small due to a condition such as a power supply or the temperature, the pulse width W at the time of no input-signal becomes large. Thus, there arises a problem that the power loss at the load such as the speaker becomes large and an amount of the heat generated from the load increases.